1. Field of the Invention
This invention relates generally to eliminating race conditions in synchronous circuits and in particular to eliminating violations of the hold time requirement of synchronous flip-flops.
2. Description of Related Art
Sequential circuits use both combinatorial circuits and storage elements. Synchronous circuits are sequential circuits in which the storage elements change their values only during discrete instants of time. Normally synchronization is achieved using a master system clock input signal throughout the system, board, or chip.
A common storage element is the D-type latch. FIGS. 1(a) to 1(d) show a logic symbol, a timing diagram, and two common implementations of the D-type latch, respectively. FIG. 1(a) shows the logic symbol of D-type latch 1310, which has data input terminal D, latch enable terminal LE, data output terminal Q, and inverted data output terminal |Q. To avoid confusion, signals on the various terminals are given the same names as the terminals themselves, whenever possible. When latch enable signal LE is active, D-type latch 1310 outputs on output terminal Q the input signal on data input terminal D. As latch enable signal LE goes inactive, D-type latch 1310 stores and outputs the input signal at the time latch enable signal LE goes inactive and ignores any changes to data input signal D until latch enable signal LE is again active. Typically, for latch enable signal LE, active is high and inactive is low; however, opposite polarity can be used so that active is low while inactive is high. D-type latch 1310 has some inherent propagation delay so that data output signal Q lags data input signal D by propagation delay T.sub.-- prop.
Specifically, as shown in FIG. 1(b), during time interval 1410, data output signal Q is equal to data input signal D after propagation delay T.sub.-- prop. During time interval 1420, latch enable signal LE is inactive and D-type latch 1310 ignores the transition of input signal D from signal V1 to signal V2. However, after rising edge 1425, when latch enable signal LE is active, data output signal Q transitions to signal V2 after propagation delay T.sub.-- prop. During time interval 1430, latch enable signal LE remains active so that any changes in data input signal D, such as the transition to signal V3, are reflected in changes to data output signal Q, which also transitions to signal V3. Since the D-type latch can change states during an entire active clock pulse such as interval 1430, the D-type latch is not well suited for use as the storage elements in synchronous circuits. Herein, an active clock pulse is the time during a clock period that the clock signal is active.
FIG. 1(c) shows a well-known D-type latch formed with four NAND gates and an inverter. Data input signal D is provided on input terminal 1111 of NAND gate 1110 and input terminal 1151 of inverter 1150. Latch enable signal LE is provided on input terminal 1112 of NAND gate 1110 and input terminal 1131 of NAND gate 1130. Output terminal 1123 of NAND gate 1120 provides data output signal Q. Output terminal 1143 of NAND gate 1140 provides inverted data output signal |Q.
FIG. 1(d) shows a well known D-type latch formed with a transmission gate (TG) and three inverters. Data input signal D is provided on data input terminal 1212 of transmission gate 1210. Latch enable signal LE is provided on control input terminal 1213 of transmission gate 1210, while an inverted latch enable signal |LE is coupled to inverted control input terminal 1211 of transmission gate 1210. Output terminal 1242 of inverter 1240 provides data output signal Q, while output terminal 1222 of inverter 1220 provides inverted data output signal |Q.
A D-type flip-flop, which changes values only during a clock transition or active edge, is better suited as the storage element of synchronous circuits than the D-type latch. FIG. 2(a) shows the logic diagram of D-type flip-flop 2410 having data input terminal D, clock input terminal CLK, data output terminal Q, and inverted data output terminal |Q. To avoid confusion, signals on the various terminals are given the same names as the terminals themselves, whenever possible. Further, the same reference numeral is used for the terminal of D-type flip-flop 2410 and the line connected to that terminal. Typically, for D-type flip-flops, rising edges are active edges and falling edges are used for inactive edges. However, in some circuits falling edges are used for active edges and rising edges are inactive edges.
On active (rising) edge 2421 (FIG. 2(b)) of clock input signal CLK, D-type flip-flop 2410 passes signal V1 on data input terminal D to data output signal Q, which changes to signal V1 after a time delay T.sub.-- cq (clock-to-out), representing the propagation delay of D-type flip-flop 2410. D-type flip-flop 2410 ignores changes to data input signal D, such as the transition from signal V1 to signal V2, until active (rising) edge 2422 of clock input signal CLK. At active (rising) edge 2422, data input terminal D is receiving signal V3. Therefore, after time delay T.sub.-- cq data output signal Q is also signal V3.
For D-type flip-flop 2410 to function properly, data input signal D must satisfy two timing constraints, a setup time and a hold time, with respect to active edges of clock input signal CLK. Setup time T.sub.-- setup is the minimum time that data input signal D must be at the proper signal level before the active clock edge. Hold time T.sub.-- hold is the minimum time that data input signal D must remain at the proper signal level after the active clock edge. If either the setup time or hold time is violated, data output signal Q of D-type flip-flop 2410 is undeterminable.
The D-type flip-flop can be implemented using many well known circuits. The exact details of each implementation are dependent upon the process technology and available semiconductor area. At the logic gate level, the only important characteristics of a D-type flip-flop are given by the timing relationships among the signals on data input terminal D, data output terminal Q, and clock input terminal CLK.
FIG. 2(c) shows a well known edge-triggered D-type flip-flop formed from six NAND gates. Data input signal D enters on input terminal 2142 of NAND gate 2140. Clock input signal CLK is coupled to input terminal 2122 of NAND gate 2120 as well as input terminal 2132 of NAND gate 2130. Output terminal 2153 of NAND gate 2150 provides data output signal Q; and output terminal 2163 of NAND gate 2160 provides inverted data output signal |Q.
FIG. 2(d) shows a well known master-slave D-type flip-flop constructed with two transmission gates and five inverters. Data input signal D is coupled to input terminal 2211 of transmission gate 2210. Clock input signal CLK is coupled to inverted control input terminal 2212 of transmission gate 2210 as well as control input terminal 2243 of transmission gate 2240. Inverted clock input signal |CLK is coupled to control input terminal 2213 of transmission gate 2210 as well as inverted control input terminal 2242 of transmission gate 2240. Output terminal 2252 provides data output signal Q while output terminal 2272 provides inverted data output signal |Q.
FIG. 2(e) shows a well known pulse D-type flip-flop. Input signal D is coupled to data input terminal 2331 of transmission gate 2330. Inverted clock input signal |CLK is coupled to input terminal 2311 of OR gate 2310 as well as to input terminal 2361 of inverter 2360. Clock input signal CLK is coupled to input terminal 2321 of AND gate 2320 as well as input terminal 2371 of inverter 2370. Output terminal 2382 provides data output signal Q. Output terminal 2352 provides inverted data output signal |Q.
A typical synchronous circuit has many instances where the data output terminal of a first storage element is coupled to the data input terminal of a second storage element. As mentioned above D-type flip-flops are the most common storage elements used in synchronous circuits. FIG. 3(a) illustrates this circuit. Data input signal D1 is coupled to data input terminal 3111 of D-type flip-flop 3110. Clock input signal CLK1 is coupled clock input terminal 3112 of D-type flip-flop 3110. Clock input signal CLK1 is also coupled to clock input terminal 3122 of D-type flip-flop 3120. However, as a result of propagation delay T.sub.-- skew, symbolized by box 3140, the signal at clock input terminal 3112 is skewed from the signal at clock input terminal 3122. For clarity, the skewed clock input signal at input terminal 3122 of D-type flip-flop 3120 is labeled CLK2. As shown in FIG. 3(b), skewing prevents transitions in clock input signal CLK1 and clock input signal CLK2 from occurring simultaneously. Data output terminal 3113 of D-type flip-flop 3110, providing data output signal Q1, is coupled to input terminal 3121 of D-type flip-flop 3120, with a propagation delay, T.sub.-- d, symbolized by box 3130. For clarity, the delayed data output signal of D-type flip-flop 3110 at input terminal 3121 of D-type flip-flop 3120 is labeled D2. Although not shown, data output signal Q1 of D-type flip-flop 3110 may pass through some combinatorial logic elements before reaching D-type flip-flop 3120. Output terminal 3123 provides data output signal Q2 to other parts of the synchronous circuit.
FIG. 3(b) shows the timing diagram of the circuit of FIG. 3(a). Clock input signal CLK1 and clock input signal CLK2 are offset by time interval T.sub.-- skew. Data output signal Q1 changes state at time interval T.sub.-- cq after the active (rising) edge of clock input signal CLK1. Data input signal D2 is offset from data output signal Q1 by time interval T.sub.-- d. For D-type flip-flop 3120 to function reliably, data input signal D2 must remain valid for at least hold time T.sub.-- hold after each active (rising) edge of clock input signal CLK2. For board level circuits, time intervals T.sub.-- skew, T.sub.-- cq, T.sub.-- d, and T.sub.-- hold are measured in nanoseconds. For chip level circuits, these time intervals would be measured in picoseconds.
Since data input signal D2 must be valid for time interval T.sub.-- hold, the following timing relationship can be derived for the circuit of FIG. 3(a) to avoid a hold time violation: EQU T.sub.-- d&gt;T.sub.-- skew+T.sub.-- hold-T.sub.-- cq.
The conventional method to fix a hold time violation in a circuit is to insert delaying elements, such as buffers or an even number of inverters, between data output terminal 3113 of D-type flip-flop 3110 and data input terminal 3121 of D-type flip-flop 3120. Typically, enough delaying elements are added to increase time interval T.sub.-- d and thereby avoid a hold time violation.
However, there are several problems with this conventional solution. If the clock frequency of the circuit is changed, time interval T.sub.-- skew, as well as other propagation delays also change. Furthermore, if the circuit is modified, such as rerouting to accommodate changes in the circuit, or shrunk such as switching an IC to a smaller geometry size, the various propagation delays as well as switching times of the flip-flops and delaying elements also change. Therefore, the delaying elements may not delay the data signal long enough to avoid a hold time violation. Finally, the insertion of the delaying elements would require rerouting of the board or chip which contains the hold time violation.
Hence there is a need for a method or circuit to correct hold time violations that does not require rerouting of the board or chip and is impervious to changes in the chip or board such as changes in clock frequencies, geometry size, layout, or routing.